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Research Papers: Implementation

Microelectronic Implementations of Fractional-Order Integrodifferential Operators

[+] Author and Article Information
Guillermo E. Santamaría

Industrial Engineering School,  University of Extremadura, Avenida de Elvas s∕n, 06071 Badajoz, Spainguillermo.santamariagaldon@telefonica.es

José V. Valverde

Industrial Engineering School,  University of Extremadura, Avenida de Elvas s∕n, 06071 Badajoz, Spainvalsan@unex.es

Raquel Pérez-Aloe

Industrial Engineering School,  University of Extremadura, Avenida de Elvas s∕n, 06071 Badajoz, Spainraquel@unex.es

Blas M. Vinagre

Industrial Engineering School,  University of Extremadura, Avenida de Elvas s∕n, 06071 Badajoz, Spainbvinagre@unex.es

J. Comput. Nonlinear Dynam 3(2), 021301 (Feb 04, 2008) (6 pages) doi:10.1115/1.2833907 History: Received June 09, 2007; Revised November 23, 2007; Published February 04, 2008

For practical applications, the fractional-order integral and differential operators require to be approximated as stable, causal, minimum-phase integer-order systems, which usually leads, in both continuous and discrete domains, to high order transfer functions. Assuming that an approximation of good quality is available for the fractional operator, efficient implementations, in both cost and speed, are required. The fast development of the microelectronics gives us the opportunity of using cheap, accurate, programmable, and fast devices for implementing reconfigurable analog and digital circuits. Among these devices, field programmable gate arrays, switched capacitor circuits, and field programmable analog arrays are used in this paper for the implementation of a fractional-order integrator, previously approximated by recursive Oustaloup’s method. The fundamentals of the devices as well as the design procedures are given, and the implementations are compared considering their simulated frequency responses, the design efforts, and other important issues.

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Copyright © 2008 by American Society of Mechanical Engineers
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References

Figures

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Figure 4

Basic circuit with one pole

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Figure 5

SCC Blocks 1–5 basic circuit

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Figure 6

SCC Blocks 1–5 basic circuit after minimizing the number of switches

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Figure 7

Switched capacitor fractional integrator complete circuit

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Figure 8

Underlying circuit of the CAM named “pole and zero bilinear filter”

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Figure 9

FPAA fractional integrator complete circuit

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Figure 10

One pole-zero basic module

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Figure 11

FPGA-based fractional integrator; complete circuit block diagram

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Figure 12

Magnitude comparison between the three microelectronic implementations

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Figure 1

Resistance emulation; parallel model

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Figure 2

ANADIGM AN13X and AN23X series block diagram

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Figure 3

FPGA general scheme gates in a single chip

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