The trend in portable products continues towards shrinking size, faster speeds, increased functionality, and, above all, low cost. Chip-scale packages are able to meet these demands of reduced board space consumption, increased functional density, and low cost while still maintaining compatibility with the existing assembly infrastructure.

A chip-scale package development effort for low to moderate I/O count devices has been initiated within Motorola using a flip-chip interposer type of design. This CSP design has been coined the JACS-Pak (Just About Chip Size Package). This work outlines a comparative analysis of various interconnect design schemes being evaluated for future versions of the JACS-Pak. Experimentally validated finite element simulation is used to predict the thermal stresses and strains induced by the manufacturing and assembly processes and thermal cycling tests. Various package design parameters are evaluated in terms of their impact on the mechanical performance of the package, and design enhancements are recommended for enhanced mechanical integrity of the chip-scale package under consideration.

This work illustrates the application of simulation during the initial design stages of the JACS-Pak, demonstrating its importance in contributing to the overall direction and success of the program.

This content is only available via PDF.
You do not currently have access to this content.