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Keywords: JEDEC
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Journal Articles

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

Hung-Jen Chang, Chau-Jie Zhan, Tao-Chih Chang, Jung-Hua Chou
Journal: Journal of Electronic Packaging
Article Type: Research Papers
J. Electron. Packag. March 2012, 134(1): 011011.
DOI: https://doi.org/10.1115/1.4005956
Published Online: March 19, 2012
.... , 2004 , “ Impact Life Prediction Modeling of TFBGA Packages Under Board Level Drop Test ,” J. Microelectron. Reliab. , 44 , pp. 1131 – 1142 . 10.1016/j.microrel.2004.03.005 12 Yeh , C. L. , and Lai , Y. S. , 2006 , “ Support Excitation Scheme for Transient Analysis of JEDEC Board...
View Article titled, Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test
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Topics: Failure, Failure analysis, Fracture (Materials), Intermetallic compounds, Lead-free solders, Printed circuit board assemblies, Solder joints, Solders, Stress, Tin
Journal Articles

Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages

Yi-Shao Lai, Chang-Lin Yeh, Ching-Chun Wang
Journal: Journal of Electronic Packaging
Article Type: Technical Briefs
J. Electron. Packag. March 2007, 129(1): 105–108.
DOI: https://doi.org/10.1115/1.2429717
Published Online: June 6, 2006
... to JEDEC drop test condition B , which features a half-sine impact acceleration pulse with a peak acceleration of 1500 g and a pulse duration of 0.5 ms . The transient finite element analysis follows the support excitation scheme and incorporates an implicit time integration...
View Article titled, Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages
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Topics: Reliability, Semiconductor wafers, Solder joints, Transient analysis
Journal Articles

Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions

Tong Hong Wang, Chang-Chi Lee, Yi-Shao Lai, Yu-Cheng Lin
Journal: Journal of Electronic Packaging
Article Type: Research Papers
J. Electron. Packag. September 2006, 128(3): 281–284.
DOI: https://doi.org/10.1115/1.2229229
Published Online: October 7, 2005
...Tong Hong Wang; Chang-Chi Lee; Yi-Shao Lai; Yu-Cheng Lin In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions...
View Article titled, Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions
Click here to open pdf in another window PDF for Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions
Topics: Boundary-value problems, Temperature, Thermal analysis, Transients (Dynamics), Vehicles, Finite element analysis, Junctions